An input buffer circuit is utilized within a semiconductor integrated circuit at a first stage to interface with devices outside of that integrated circuit. Typically, to allow for compatible interconnection of the integrated circuit with outside devices, the input buffer circuit has a requirement or specification that it operates at a certain input threshold voltage (V.sub.TH). Thus, for example if the power supply voltage (V.sub.DD) that the particular circuit is to operate is 5 volts, the V.sub.TH would be typically 1.5 volts. Hence, with such an input threshold voltage V.sub.TH, for the signal to be provided at the input of the integrated circuit to be at a high value, the voltage value of the signal would be 2.0 volts or above (typically 3.0 volts). For the signal at the input of the integrated circuit to be at a low value, the voltage value of the signal would be 0.8 of a volt or below (typically 0 volts or ground).
A typical prior art input buffer circuit comprises a simple inverter. The inverter comprises a p-channel pull-up transistor coupled to an n-channel pull-down transistor. The source of the p-channel transistor is coupled to a supply voltage V.sub.DD, while the source of the n-channel pull-down transistor is coupled to a ground voltage V.sub.SS. It is desirable to have an inverter with high drive potential so that it can drive large capacitive load at the output. The ability of the inverter to provide a high drive potential at the output of the input buffer circuit is determined by the size of the transistors. An increase in the size of the transistors results in an increase in the drive potential.
On the other hand, static ICC, which is the current drawn by the inverter when the input at static condition (2.0 volts or above), increases as the size of the transistors increases. Static ICC must be minimized because it undesirably increases the power consumption of the circuit.
Furthermore, in order to achieve the desired input threshold voltage V.sub.TH of 1.5 volts, even though a typical n-channel transistor of the same size as the p-channel transistor is twice the strength of such a device by virtue of higher carrier mobility in a n-channel transistor, the n-channel device must be approximately three and one-half (3.5) times larger than the p-channel device. Hence, as the size of the p-channel transistor is increased in order to provide an increase in drive potential, there must be a corresponding increase in size of the n-channel transistor by 3.5 times in order to maintain the proper input threshold voltage V.sub.TH. This increase in size will also cause a corresponding increase in the amount of static current ICC drawn by the input buffer circuit when the circuit is in the static high condition (typically 3.0 volts), resulting in an undesirable increase in the power consumption. Accordingly, given the inverter input threshold voltage requirement of 1.5 volts, a trade-off exists between achieving high drive potential and mininizing power consumption.
Another problem associated with this type of arrangement is that due to the sizing consideration of the n-channel and p-channel transistors as mentioned above (i.e. n-channel must be 3.5 times bigger than the p-channel), in conjunction with the fact that n-channel transistors are inherently twice as strong as p-channel transistors, the strength of a n-channel transistor to a p-channel transistor is approximately at a ratio of seven to one. Since the weak p-channel transistor is responsible for driving the inverter output when the output makes a low-to-high transition, the output is slow and the driving capability is limited during such a transition. One way to alleviate this problem is to increase the driving capability of the input buffer by coupling it in series with a second inverter. However, an additional inverter would cause additional gate delay which undesirably slows down the circuit.
An alternate prior art input buffer attempts to address these problems by using a pull-up n-channel transistor and a pull-down n-channel transistor to provide the needed output current drive capability. A weak pull-up p-channel transistor is also used to pull the output to rail (i.e. V.sub.DD or V.sub.SS) and hold it there. The pull-up n-channel transistor is driven by an inverter which is driven by the input in order to obtain the correct logic for the pull-up n-channel transistor. In doing so, the output drive capability is increased because both output drivers can be comparably sized. In particular, the pull-up n-channel transistor can now be made much stronger as compared to the single inverter input buffer. Also, the input threshold voltage V.sub.TH of the inverter that drives the pull-up n-channel transistor is no longer limited to the ratio 3.5 to 1 that limits the single inverter input buffer. This is because the input threshold voltage V.sub.TH is now a function of all the elements together, not just the n-channel and p-channel transistors of the single inverter. Therefore, there is an incremental gain in speed due to the increased outpour current drive and the ability to more optimally size the inverter driving the pull-up n-channel transistor. However, this second prior art input buffer still does not provide adequate speed for some high-speed integrated circuit applications.
Hence, there is a long felt bull unsatisfied need for an input buffer circuit that has increased speed performance over prior art input buffer circuits. In addition, the input buffer circuit should be one that has a drive potential that is at least the equivalent of the prior art devices while maintaining low power consumption requirements associated therewith.
Accordingly, the present invention is directed toward an input buffer circuit which has increased speeds over prior art circuits. In addition, such a circuit will not be any more suceptable to noise problems associated with ground bounce and the like.